Transistors are used in the integrated circuits (ICs). FIG. 1a shows a portion of a device 100 having a metal oxide semiconductor (MOS) transistor 110 formed on an active region of a substrate 102. A well 104 is located in the active region of the substrate. Shallow trench isolations 108 are used to isolate the active region from other device regions (not shown). The transistor has source/drain (S/D) regions 152a-b adjacent to a gate 130, which includes a gate electrode 134 over gate dielectric layer 132. Located on the gate sidewalls are dielectric spacers 142. Metal silicide contacts 162 and 164, such as nickel or nickel alloy silicide contacts, are provided on the surface of the substrate in the S/D regions and gate electrode.
We have discovered that during processing, the dielectric spacers may be over etched, resulting in spacer pulldown. The spacer pulldown exposes portions of the gate sidewalls. Thus, the thickness of the nickel or nickel alloy silicide contact formed is thicker than expected. In addition, we have discovered that excess Ni layer with highly diffusive Ni atoms will diffuse into the gate and form nickel or nickel alloy silicide filaments 167 as shown in FIG. 1a. FIG. 1b shows a TEM image of a transistor exhibiting such phenomenon. As shown in FIGS. 1a-b, nickel or nickel alloy silicide filaments are formed over the spacers. These nickel or nickel alloy silicide filaments can lead to short circuit between the gate and source/drain contact plugs formed thereafter due to contact misalignment, negatively affecting device performance or functionality.
In view of the foregoing, it is desirable to provide transistors with metal silicide contacts without filament formation.